This application claims the benefit of German application number 101 21 309.3, filed May 2, 2001, currently pending, the disclosure of which is incorporated herein by reference in its entirety.
The invention relates to a test circuit for testing a circuit to be tested, in particular a test circuit for testing a synchronous memory operating at a high frequency.
FIG. 1a shows a test arrangement according to the prior art. A circuit to be tested (DUT: Device Under Test) is tested in respect of its functionality by an external test unit. The circuit to be tested is, for example, a synchronous memory module containing a multiplicity of memory cells. The external test unit applies control signals for testing the synchronous memory module via a control bus and addresses the memory cells to be tested within the memory module via the address bus. A test data generator contained in the external test unit generates test data patterns which, in a writing operating mode, are applied via a data bus to the circuit to be tested and are written to the addressed memory cells. Afterward, in a reading operating mode, the data are read out again from the addressed memory cells and transmitted back to the external test unit via the data bus. The test unit compares the read-out test data internally with reference test data and identifies defective memory cells on the basis of discrepancies between the reference test data and the read-out data.
In order to increase the maximum possible data transmission rate in the case of point-to-point data connections, the signal lines of the data bus, which comprises d data signal lines, for example, are designed as differential signal lines. In this case, for each data signal, in parallel the corresponding inverted data signal is passed via a dedicated signal line.
FIG. 1b shows an example of a data line pair of the data bus between the circuit to be tested DUT and the external test unit. The data line pair of the differential data bus has a first data signal line for the transmission of a data signal sig and a second data signal line for the transmission of a data signal {overscore (sig)} inverted with respect thereto. The two illustrated data signal lines of the data line pair between the circuit to be tested DUT and the test unit have a length L.
The differential signal transmission makes it possible for the input and output stages of the circuit to be tested DUT and of the test unit to be constructed simply in terms of line technology, at the same time the input and output stages and also the transmission link being insensitive to jitter of the signal edges and drifts of the DC voltage levels.
The relatively long data signal lines between the test unit and the circuit to be tested DUT give rise to signal propagation time delays of the data signals and to signal propagation time differences between the transmitted data signal and the transmitted inverted data signal with respect thereto. The propagation time differences are a consequence of different line lengths of the two data lines of a data line pair, different parasitic capacitances or inductances and different manufacturing tolerances. Since, in the case of the test arrangement illustrated in FIG. 1b, signal propagation time differences between the data signal and the data signal transmitted in inverted form with respect thereto cannot be calibrated out, these signal propagation time differences lead to losses in the temporal accuracy of the entire test arrangement and thus to yield losses during testing. The additional inaccuracy effected by the signal propagation time differences is in excess of 50 pico seconds in many cases. When testing high-frequency memory modules which operate with clock frequencies of a few hundred megahertz, such signal propagation time delays cause test errors.
Therefore, the test arrangement illustrated in FIG. 2 was proposed. In order to compensate for the signal propagation time differences brought about by the data signal lines, in some instances having a length measured in meters, the connections and also the terminal electronics, in the test arrangement illustrated in FIG. 2 the evaluation instants of an input stage are set by a calibration circuit KAL integrated in the test unit. The input stage contains differential amplifiers which compare the received data signals with a static comparator voltage Vcom, generated by a comparator voltage generator KONP.
The disadvantage of the test arrangement according to the prior art as shown in FIG. 2 is that it is highly susceptible to the timing jitter and to DC or DC voltage level drifts.
FIGS. 3a to 3c show the calibrateable test arrangement according to the prior art in accordance with FIG. 2 and the associated signals for elucidating the problems occurring here.
A data signal SIGDUT output by the circuit to be tested DUT is received with a certain signal delay as signal SIGtester by the input stage of the external test unit and is compared with a comparator voltage Vcomp by a differential amplifier. In the same way, the circuit to be tested DUT outputs an inverted data signal {overscore (SIG)}DUT, which is received as inverted data signal {overscore (sig)}tester by the input stage of the external tester unit and is compared with the set comparator voltage Vcomp as threshold value by a second differential amplifier.
FIG. 3b shows, by way of example, an alternating data sequence 101010 and the associated output data signals at the output data driver of the circuit to be tested DUT.
FIG. 3c shows, by way of example, how this output data output signal is received by an input stage of the external test unit on account of a DC voltage fluctuation. If the received data signal SIGtester is above the comparator voltage Vcomp and, at the same time, the data signal SIGtester inverted with respect thereto lies below the comparator voltage, the input stage outputs a logic high datum H for further data processing. Conversely, if the received data signal is lower than the comparator voltage level and, at the same time, the inverted data signal is above the comparator voltage level, the input stage of the test unit outputs a logic zero L for further data processing.
If both the received data signal and the inverted data signal lie below the comparator DC voltage level, this is interpreted as a data transmission error F. The same applies if both the received data signal and the data signal inverted with respect thereto lie above the comparator DC voltage level.
In the example illustrated in FIG. 3c, the potential of the data signal levels is pulled down on account of a DC voltage drift, so that, from the instant t2, both the received data signal sigtester and the inverted data signal {overscore (Sigtester)} with respect thereto lie below the comparator DC voltage level and, consequently, a data transmission error F is identified. A test unit with a calibrateable input stage for compensating for signal propagation time differences between the data signal lines of a data signal line pair is thus highly sensitive to potential fluctuations on the signal lines, so that test errors can occur.
The test arrangement according to the prior art as illustrated in FIG. 1 is relatively insensitive to the potential fluctuations on the data signal lines, but the signal propagation time differences between the data lines of a data line pair lead to test errors. By contrast, in the case of the test arrangement according to the prior art as illustrated in FIG. 2, said propagation time differences are compensated for by a calibration circuit, but this procedure leads to test errors on account of DC voltage level fluctuations on the data signal lines, as explained in connection with FIGS. 3a to 3c. 
Therefore, the object of the present invention is to provide a test circuit for testing a circuit which avoids test errors on account of signal propagation time differences and, at the same time, is insensitive to potential fluctuations on the data signal lines.
This object is achieved according to the invention by means of a test circuit having the features specified in Patent claim 1.
The invention provides a test circuit for testing a circuit, having
a test data generator, which generates test data in a manner dependent on data control signals which are received via data control lines from an external test unit;
a data output driver for outputting the generated test data via data line pairs of a differential data bus to the circuit to be tested;
a data input circuit for receiving data that are read from the circuit to be tested and transmitted via the data line pairs of the differential data bus;
a data comparison circuit, which compares the generated test data and the read-out data and, in a manner dependent on the comparison result, transmits an indication signal, which indicates whether the circuit to be tested is functional, to the external test circuit via an indication signal line;
each data line pair of the differential data bus, between the circuit to be tested and the test circuit, having a first data signal line for the transmission of a data signal and a second data signal line for the transmission of a data signal inverted with respect thereto, and the two data signal lines being short in order to minimize signal propagation time differences between the transmitted data signal and the transmitted inverted data signal.
The test circuit according to the invention has the advantage that a calibration circuit which calibrates out the signal propagation time differences between the data signal lines is not necessary.
In a preferred embodiment of the test circuit according to the invention, said circuit contains an address generator, which generates address signals for the circuit to be tested in a manner dependent on address control signals which are received via address control lines from the external test unit.
The generated address signals are preferably transmitted from an address signal output driver of the test circuit via address line pairs of a differential address bus to an address signal input driver of the circuit to be tested.
In this case, each address line pair preferably has a first address signal line for the transmission of an address signal and a second address signal line for the transmission of an address signal inverted with respect thereto.
The two address signal lines of each address line pair are preferably designed to be short in order to minimize signal propagation time differences between the transmitted address signal and the transmitted inverted address signal.
In a preferred embodiment of the test circuit according to the invention, said test circuit contains a frequency multiplication circuit, which receives the clock frequency of a low-frequency clock signal received from the external test unit and multiplies it by a specific factor in order to generate a high-frequency clock signal for the circuit to be tested.
Furthermore, the test circuit according to the invention preferably has an internal control circuit, which generates internal control signals for driving the data input driver, the data output driver and the address signal output driver in a manner dependent on control signals which are received with a low clock frequency from the external test unit.
In a preferred embodiment, the test circuit according to the invention is integrated in the circuit to be tested. The test circuit according to the invention is preferably used for testing synchronous memories, in particular synchronous DRAM memories which operate with a very high operating clock frequency of hundreds of megahertz.
A preferred embodiment of the test circuit according to the invention is described below with reference to the accompanying drawings in order to elucidate features that are essential to the invention.